Memristive devices with analog resistive switching characteristics are widely investigated nowadays for electronic synapses that facilitate memory and learning in neuromorphic computing hardware. It is therefore essential to understand and optimize the incremental switching behavior of the cells in order to enhance the functionality of memristive neural networks. Here we report a systematic study on the analog switching of bilayer oxide based memristive synapses and show that transition metal oxides with rich intermediate phases, such as WOx, are able to provide larger number of conductance states compared with oxides with few intermediate phases such as TaOx and HfOx. This could be attributed to the intrinsically different electrical properties of the intermediate phases that jointly contribute to the change of device conductance, in addition to that caused by the varied geometry of filaments during programming. Controlled studies adopting different materials, compositions and sequences of oxide bilayers reveal that the analog switching is mainly dominated by the switching layer, thus providing clues to the optimization of memristive devices for future neuromorphic applications.

The development of smart, scalable, and power efficient computers relies on innovative technologies that can distribute memory alongside processing, such as emerging neuromorphic computing and in-memory logic technologies. Here, a type of vertical 3-terminal oxide based nanoionic device capable of implementing heterosynaptic plasticity and nonvolatile Boolean logic simultaneously is demonstrated. The heterosynaptic plasticity endows the devices with facilely tunable synaptic kinetics via tailoring modulatory signals, which is shown to be crucial for achieving optimized learning scheme, therefore offering promising building blocks for neuromorphic computing. Furthermore, it is demonstrated that these heterosynaptic devices can simultaneously be utilized to implement nonvolatile Boolean logic with improved efficiency compared with existing approaches, therefore implying in-memory computing potentialities. The heterosynaptic devices with such multifunctionality thus hold great potential for next-generation non-von Neumann computing applications.

Brain-inspired neuromorphic computing is expected to revolutionize the architecture of conventional digital computers and lead to a new generation of powerful computing paradigms, where memristors with analog resistive switching are considered to be potential solutions for synapses. Here we propose and demonstrate a novel approach to engineering the analog switching linearity in TaOx based memristors, that is, by homogenizing the filament growth/dissolution rate via the introduction of an ion diffusion limiting layer (DLL) at the TiN/TaOx interface. This has effectively mitigated the commonly observed two-regime conductance modulation behavior and led to more uniform filament growth (dissolution) dynamics with time, therefore significantly improving the conductance modulation linearity that is desirable in neuromorphic systems. In addition, the introduction of the DLL also served to reduce the power consumption of the memristor, and important synaptic learning rules in biological brains such as spike timing dependent plasticity were successfully implemented using these optimized devices. This study could provide general implications for continued optimizations of memristor performance for neuromorphic applications, by carefully tuning the dynamics involved in filament growth and dissolution.

Graphene is considered to be one of the most promising materials in post-silicon electronics due to its remarkable geometric structure and physical properties. The realization of controllable and abrupt p–n junctions is crucial for the applications of graphene in nanoelectronics. In this paper, a novel step-dielectric design to modulate the doping profile in monolayer graphene is proposed and experimentally demonstrated. Resistance–voltage transfer characteristics of the fabricated device show the presence of two resistance peaks, verifying the formation of p–n junctions under certain bias conditions. Based on this technique, junctions with appreciable abruptness and controllability over the junction properties could be simultaneously obtained. In addition, mobility values of this device are extracted to be larger than 5000 cm2 V−1 s−1 due to the high quality of the gate oxide/graphene interfaces. This proposed technique would facilitate the development of novel devices composed of graphene p–n junctions.

The deteriorated radiation effects of very deep-sub-micron (VDSM) MOS transistors with multi-finger are experimentally investigated for the first time. The results show that due to the interaction between reverse narrow channel effect and radiation induced edge effect, multi-finger transistors are more sensitive to radiation in comparison with standard MOSFETs. Larger threshold-voltage shift and higher leakage current are observed. The mechanisms responsible for the effects are briefly discussed. The results demonstrate that special radiation hardening technology should be adopted for multi-finger transistors operating in the radiation environment.

A novel vertical channel self-aligned split-gate floating-gate flash memory (VSAS_FG) was proposed and experimentally demonstrated for the first time. The floating-gate of VSAS_FG can be self-aligned realized without additional mask. Moreover, the VSAS_FG has higher scalability since the cell area of vertical channel device is independent on gate length. With enhanced electrical fields for programming and erasing, the fabricated VSAS_FG can achieve ∼10 μs programming time and ∼10 ms erasing time. The cycling endurance and the bake retention were also investigated. The experimental results demonstrate the feasibility of the VSAS_FG concept as a promising candidate for low-power, high-density flash memory application.