Trigger voltage walk-out phenomenon is found in SOI LIGBT’s under repetitive ESD stresses. Such a characteristic would cause an IC to be susceptible to the risk of exceeding the ESD design window and thus resulting in core circuit damages when the LIGBT is served as an ESD protection device in the SOI process. This trigger-voltage walk-out phenomenon is investigated in this paper, and both the experimental evidences and device simulation results are presented to offer the insight of the underlying physical mechanism.

An all-digital coherent-like binary frequency shift keying (BFSK) demodulation based on the use of a multi-bit shift register, two multi-bit XOR gates and a mean value filter is presented. The demodulator is fabricated in SMIC 65-nm CMOS process with a die area of 0.015 mm2. The demodulator consumes 1.44 mW with 1.2 V of voltage supply and 32 MHz of sample clock. The measured bit error ratio (BER) performance is better than that of other non-coherent demodulators. The proposed demodulator exhibits better performance in terms of composite indicator compared to other demodulators. Another advantage of the all-digital demodulator defined using Verilog HDL is that it can also be implemented on Field Programmable Gate Array (FPGA) platform rapidly to recover FSK signals with different carrier frequencies and data rates. These results make the all-digital demodulator suitable for the application in communication and consumer electronics.

In this paper, on-resistance (Ron) degradation induced by off-state avalanche breakdown in a 40 V LDMOS with step-shaped gate oxide (SGO–LDMOS) is investigated. Ron unexpectedly decreases at the beginning of stress, which is different from the phenomenon described in works on LDMOS with uniform gate oxide (UGO–LDMOS). Based on the experiment data and TCAD simulation results, two degradation mechanisms are proposed. That is the generation of positive oxide-trapped charges at the bird’s beak region near source and formation of interface state at the bird’s beak region near source and drain respectively.Highlights► Degradation induced by off-state avalanche breakdown in SGO–LDMOS is investigated. ► The anomalous phenomenon of on-resistance Ron degradation is disclosed. ► Based on the experiment and TCAD simulation, two degradation mechanisms are proposed.

•A new diode string structure has been developed for 65-nm ESD protection.•It possesses a 30% lower clamping voltage, a 15% lower overshoot voltage under very fast ESD pulse.•It has a faster turn-on speed of 0.8 ns, and a low intrinsic capacitance of 28 fF.•It is successfully implemented in a low-noise amplifier (LNA) and achieved a ±2.5 kV human body model (HBM) ESD level.Diode strings are frequently used for electrostatic discharge (ESD) protection of high-speed and radio-frequency (RF) I/O pins due to their low capacitance, tunable trigger voltage and simplicity of design, but they always exhibit a high clamping voltage due to the series connected on-resistance, which limits their applications in low-voltage ICs. In order to reduce to their clamping voltage, a new structure of diode string has been developed and investigated by 2-D electro-thermal simulations. Experimental results show that the improved diode string possesses a 30% lower clamping voltage, a 15% lower overshoot voltage under very fast ESD pulse, a faster turn-on speed of 0.8 ns, and a low intrinsic capacitance of 28 fF. The improved diode string is successfully implemented in a fully-integrated 3–10 GHz ultra-wide band (UWB) low-noise amplifier (LNA) based on a 65 nm CMOS process, which is shown to have minimal effects on the RF performances and achieves a ±2.5 kV human body model (HBM) ESD level.

This paper presents device optimization and physical analysis based on gate-grounded NMOS (GGNMOS) and n-channel lateral DMOS (nLDMOS) devices manufactured in a 0.35 μm 5 V/30 V high-voltage BCD process. The multiple body pick-up technique has been investigated in detail for the GGNMOS, and the robustness and effectiveness of the LDMOS device is optimized by tuning the drain contact to gate space (DCGS) and increasing the body resistance. Finally, the trigger voltage walk-in effect is observed for the nLDMOS device and is studied by comprehensive simulation and TLP tests.

A novel Substrate-Engineered Gate-Grounded NMOS (GGNMOS) structure with very low trigger voltage is proposed to protect the ultra-thin gate oxide effectively in nanoscaled integrated circuits. This device is designed and verified in a 65 nm CMOS process. With increased substrate resistance and pumped triggering current provided by power bus controlled PMOS, this structure features a significantly reduced trigger voltage of 2.8 V and an enhanced uniform conduction of multi-fingers. The failure current can be improved by 23.5% compared with traditional GGNMOS.Highlights► Substrate-Engineered Gate-Grounded NMOS structures are designed in 65 nm process. ► Substrate-triggering technique and dynamic substrate resistance technique are used. ► It features a low trigger voltage of 2.8 V. ► Failure current can be improved by 23.5% due to uniform conduction of multi-finger.

The hot-carrier-induced (HCI) degradations of silicon-on-insulator (SOI) lateral insulated gate N-type bipolar transistor (NLIGBT) are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. The substrate current Isub and on-state resistance Ron at different voltage stress conditions are measured to assess the HCI effect on device performance. The electric field and impact ionization rate are simulated to assist in providing better physical insights. And charge pumping current is measured to determinate the front-gate interface states density directly. The degradation mechanisms under different gate voltage stress conditions are then presented and summarized.

The merged and compact MOS-triggered SCR devices have been compared and investigated in a 0.13 μm CMOS process. From experimental results, the turn-on time of compact MOS-triggered SCR has been improved from ∼7.2 ns of merged MOS-triggered SCR to ∼4 ns. Compared to merged MOS-triggered SCR devices, the compact MOS-triggered SCR devices can achieve a lower trigger voltage, a faster turn-on speed, a lower on-resistance, a lower clamping voltage and a higher failure current.

Residual current circuit breakers (RCCB) is the equipment which protect human body from an electric shock, there is close relation between RCCB and human safety. However, shortages still exist. Current RCCB tend to cause nuisance tripping due to their sensitive reaction to the interference signal in the actual power grid. So, the RCCB cannot work at the crucial moment effectively. This paper analyzes the impact to the RCCB from the general interference signal and induced interference signal in power grid, and this paper also introduces a new technique—10 ms non-actuating time technique, which is used to stand aside the interference signal. This technique with delay time protection and other anti-interference technique are integrated into a special RCCB IC chip, which is fabricated in a mixed-signal 0.5 µm CMOS process in CSMC. The test results verify great improvement in RCCB performance. Additionally, this paper analyzes the disadvantage of the active national standard referring to RCCB in China and presents some suggestions for the improvement.

A novel polysilicon-assisted silicon-controlled rectifier (SCR) is presented and analyzed in this paper, which is fabricated in HHNEC’s 0.18 μm EEPROM process. The polysilicon-assisted SCRs take advantage of polysilicon layer to help by pass electro-static discharge (ESD) current without occupying extra layout area. TLP current-voltage (I-V) measurement results show that given the same layout areas, robustness performance of polysilicon-assisted SCRs can be improved to 3 times of conventional MLSCR’s. Moreover, one-finger such polysilicon-assisted SCRs, which occupy only 947 μm2 layout area, can undergo 7-kV HBM ESD stress. Results further demonstrate that the S-type I-V characteristics of polysilicon-assisted SCRs are adjustable to different operating conditions by changing the device dimensions. Compared with traditional SCRs, this new SCR can bypass more ESD currents and consumes smaller IC area.